I work at AMD Research on microarchitecture techniques to reduce on-chip and off-chip data movement (i.e., NIC to CPU, CPU/GPU to memory, and within memory). My research on memory architecture has resulted in a publication at AMD GTAC 2020.

I research energy-efficient HBM architecture for AI workloads. My research on HBM design for sparse, irregular applications has resulted in a best paper finalist at AMD GTAC 2021 and multiple invention disclosures.

My current focus is on accelerating general matrix multiplications (GEMMs) and tensor contractions via co-design of dataflow, GPU microarchitecture, and the memory hierarchy. Target applications include AI workloads such as large-language models (LLMs) and deep learning recommendation models (DLRMs).

Previously, I researched topics on power-aware computing and profiling tools under DOE's star forward programs. A one-of-a-kind GPU profiler that I co-developed as a part of this effort has been used to (i) optimize major exascale HPC and AI applications, including LLM implementations from hyperscalers, and (ii) enhance the gem5 simulator via comprehensive extraction of GCN instruction latencies.